1. Field of the Invention
The present invention relates generally to integrated semiconductor memory devices, and more particularly, to techniques for fabricating and designing charge storage capacitors in Dynamic Random Access Memory arrays.
2. Description of the Related Art
A dynamic random access memory (DRAM) cell is made from a silicon wafer using state-of-the-art semiconductor processing techniques. Typically, a DRAM cell comprises a charge storage capacitor coupled to an access device such as a field effect transistor (FET). The FET functions to charge or discharge the capacitor, thus affecting the logical state defined by the stored charge.
In the continuing trend to higher memory capacity, the packing density of capacitors (storage cells) must increase, yet each will maintain required capacitance levels. This is a crucial demand of DRAM fabrication technologies if future generations of expanded memory array devices are to be successfully manufactured.
One method of maintaining as well as increasing total charge storing capacity in densely packed memory devices is through the use of stacked capacitor cell (STC) design. In general, a stacked capacitor structure can be manufactured by sequential deposition of capacitor members over the gates of the FET device, e.g., DRAM word lines, and over the active areas where the electrical connection between the access device and the capacitor occurs. The capacitor structure generally includes a lower conductive layer (storage plate), an insulator layer and an upper conductive layer (reference plate). The upper conductive layer and the lower conductive layer are conventionally made of polysilicon material. The insulator may be made of oxide, silicon nitride, ONO or other dielectric layers interposed between the capacitor plates. In conventional stacked capacitor structures, a polysilicon plug (poly plug) is generally formed to provide an electrical connection between the capacitor structure and the active area. Thus, to prevent any current leakage between the poly plug and the gate electrode, the gate electrode must be effectively isolated by the sidewall spacers and top spacers. To provide adequate etch selectivity, as will be described below, silicon nitride is commonly used as the insulating spacer material. In this respect, the poly plug fills the gap between the nitride sidewall spacers of the transistor gates or word lines on either side of the active area.
In stacked capacitor designs, the capacitor should cover nearly the entire area of a cell and vertical portions of the cell, such that a large bottom electrode surface area contributes to the total charge storing capacity of the cell. A process that permits the fabrication of a storage node contact and the cell itself requires the use of various masking and etching steps. Conventionally, a relatively thick insulating layer must be provided. As thick silicon nitride layers generally introduce excessive stress to the wafer, the insulating layer generally comprises an oxide such as borophosphosilicate glass (BPSG). Contact openings are etched through the oxide and expose the poly plug or active areas. Mask materials serve to protect surrounding devices from the unwanted effects of both the depositing materials and the etchants used. However, considering the minute size of these contact openings, this is not an easy task in the semiconductor industry.
In the past, using conventional lithographic techniques, mask alignment tolerances and the deposition processes have significantly limited both the degree of simplification and the degree of size reduction in DRAM applications. Nevertheless, once the potential advantages of self-aligned fabrication techniques are realized by the semiconductor industry, limitations caused by mask alignment tolerances are generally overcome. It is understood that commonly used materials, such as silicon nitride, silicon oxide, silicon, polysilicon and photoresist, all have different etch removal rates when exposed to various etchants. Self-aligned processing techniques use the selective etchability of the different layers to align and form desired openings in the masking layers to thereby expose the contact regions.
In capacitor fabrication, a selective etching process is used to etch a contact opening through the insulating layer (usually oxide). Since the active areas are located between the word lines (gates), the etch process should be selective with respect to sidewall spacers of the gates, such that the opening defined by the mask may be wider than the inter-gate spacing without harming the gates. Specifically, the spacer has a slower etch rate than the masking material so that the opening can be defined by using an etchant that will quickly remove the oxide without etching much of the spacer. Hence, the photoresist pattern that is used to define the contact opening need not be precisely aligned in the process. Consequently, the self aligning process is very attractive for ULSI applications where small device dimensions require very tight photolithographic tolerances.
However, as the dimensions of individual memory cells in a DRAM array continue to shrink, the efficiency and the reliability of the conventional self aligned processes have dramatically decreased. With these smaller spaces, the chances for leakage between the contacts, transistors and capacitor components has increased.
One of the problems with the conventional self aligned process is the requirement of using a spacer material which is resistant to etchants which attack the insulating layer. As discussed above, the spacers not only protect the polysilicon gate from the etchants, they also provide electrical isolation between the gate and the contact region. Therefore, with such small device dimensions, even a small amount of damage to the spacers can increase the likelihood of an electrical short between the gate electrode and the conductive polysilicon-plug. Accordingly, conventional self-aligned technology strictly depends on the selectivity with which the materials may be etched. As previously mentioned, silicon oxide is the most common insulating material for isolating devices in an integrated circuit. As oxide may be selectively etched against silicon nitride, nitride has been generally preferred for gate spacers. In fact, the prevalence of conventional self-aligned contacts through silicon oxide has made nitride practically irreplaceable for spacer structures in prior art processes.
However, the reliance of conventional processing upon the selectivity of etching against the spacers results in some etching even into nitride spacers, since it is difficult to select against both the nitride spacers and the silicon substrate. Furthermore, the differential height of the contact over the spacers and over the substrate leads to overetching into the nitride spacers. Such damage leads to shorting problems, especially as device dimensions continue to shrink.
Furthermore, silicon oxide, for example, possesses many advantageous features over silicon nitride as a spacer material. Some of these advantages are the simplified processing and soft dielectric characteristics of the silicon. Additionally, oxide spacers induce less stress over the substrate and the neighboring gate stack layers compared to nitride spacers. As is well known in the art, nitride is a rigid and brittle material. When deposited on materials having less rigidity, the nitride increases the stress level in the neighboring materials and hence causes stress-induced defects.
Another major problem of conventional processing techniques for manufacturing capacitors is the number of photolithographic or masking steps used throughout the process. In general, three masking steps are required to manufacture a prior art capacitor. The first masking step is used to define a buried contact opening to reach the active areas. The second mask is used to define the bottom or storage electrode and the final mask defines the upper or reference electrode.
However, in today's very competitive and high volume semiconductor industry, the number of masking steps in device fabrication sets the criteria for product quality and reliability as well as manufacturing costs. It is well known in the art that reducing the number of masking steps in integrated circuit manufacturing not only reduces the manufacturing cost and time but also increases the reliability and quality of the end product, since fewer masking steps produce fewer defects. This is also true for DRAM capacitor fabrication. A process that not only permits more compact capacitor structures, i.e., self-aligned fabrication process, but also reduces the number of fabrication steps, particularly the masking steps, would be a significant advantage in the art of DRAM capacitor fabrication.
Thus, there is an increasing need in the industry for an improved contact formation in integrated capacitor fabrication process that provides the advantages of self-alignment while permitting a wide variety of materials as masking and spacer material and minimizing overetch damage into the word line or gate spacers. The process should also advantageously require fewer masking steps than prior art processes.